FIG. 1 illustrates a flow of manufacturing process of a semiconductor integrated circuit device (corresponding to FIG. 2 of a non-patent document 1, i.e., “Delay Defect Screening for a 2.16 GHz SPARC64 Microprocessor”, Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraidel, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi, Fujitsu Limited, Fujitsu laboratory, 0-7803-9451-8/06, 2006, IEEE, 4A-1, pages 342-347)
As depicted in FIG. 1, generally speaking, the flow can be divided into a process of manufacturing and testing of an LSI chip (simply referred to as a “chip” or “bare chip” hereinafter) for a semiconductor integrated circuit device (S1-S3), and a process of packaging the chip, testing a thus-obtained semiconductor integrated circuit device package and shipping the semiconductor integrated circuit device package (S4-S9).
In the process of manufacturing and testing of the chip (S1-S3), a chip manufacturing process S1, a functional test S2 and a delay defect screening process S3 are carried out.
In the chip manufacturing test S1, a semiconductor integrated circuit device bare chip is manufactured. In the functional test S2, a basic function of the semiconductor integrated circuit device bare chip thus manufactured is then verified.
It is noted that “bare chip” indicates an LSI chip before packaging.
In the delay defect screening process S3, a so-called delay test is carried out on the semiconductor integrated circuit device bare chip for which the basic function has been verified in the functional test process S2. In the delay test, a test such as that which will be described with reference to FIGS. 2A and 2B (corresponding to FIG. 3 of the above-mentioned non-patent document 1) is carried out. Thus, it is verified whether an operating speed of semiconductor integrated circuit device bare chip meets a prescribed requirement.
In the process of packaging the above-mentioned semiconductor integrated circuit device bare chip, testing a thus-obtained semiconductor integrated circuit device package and shipping the semiconductor integrated circuit device package (S4-S9), an external inspection process S4, a packaging process S5, a burn-in process S6, a speed binning process S7, a unit test process S8, and running test process S9 are carried out.
In the external inspection process S4, an external appearance of the semiconductor integrated circuit device bare chip is inspected. In the packaging process S5, the semiconductor integrated circuit device bare chip having undergone the external inspection process S4 is mounted in a package. Thus, a semiconductor integrated circuit device package (also referred to as a semiconductor integrated circuit device) is manufactured.
In the burn-in test process S6, an environmental applicability verification test such as burn-in, aging and so forth is carried out on the semiconductor integrated circuit device package.
In the speed binning process S7, a selection is made from semiconductor integrated circuit device packages having undergone the burn-in test process S6. Here, for each of the semiconductor integrated circuit device packages, a suitable operating frequency is determined, and therewith, a selection is carried out from the semiconductor integrated circuit device packages.
In the unit test process S8, the thus-selected semiconductor integrated circuit device package is operated under actual operating conditions, and thus, it is verified that the semiconductor integrated circuit device package operates properly under the actual operating conditions.
In the running test process S9, for the semiconductor integrated circuit device package having undergone the unit test process S8, it is verified whether the semiconductor integrated circuit device package can properly carry out such an operation that will be carried out under a condition where the semiconductor integrated circuit device package will be installed in an apparatus as a final product (such as a server). Such a verification process is called “product test” hereinafter, and includes a “verification process for an operation delay after packaging” described later. After the semiconductor integrated circuit device package undergoes the running test process S9, the semiconductor integrated circuit device package is shipped.
Japanese Patent Application No. 2006-253651, and Japanese Laid-Open Patent Applications Nos. 2003-43109, 2005-83895 and 2005-257654 also discusses related arts.